1. Field of the Invention
The present invention relates to an apparatus and method for manufacturing semiconductor devices. More particularly, the present invention relates to an apparatus and method for manufacturing semiconductor devices having hemispherical grains (HSG) on the lower electrode of the capacitor of a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are becoming more highly integrated as developments progress from the 16M and 64M DRAM (Dynamic Random Access Memory) devices, to the 256M and greater capacity memory devices. Even as the sophistication and capacity of the device itself increases, there are ongoing efforts to keep the devices as small as possible for subsequent implementation in miniature electronic products. In view of this desire to obtain smaller devices, the space for each memory cell must be reduced accordingly.
Generally, each memory cell unit of a DRAM is composed of a MOS (Metal Oxide Semiconductor) transistor and a capacitor. Even with the reduced cell size as described above, the memory device must still have a sufficient minimum threshold capacitance in order to function properly.
A semiconductor capacitor includes a lower electrode (storage electrode) and an upper electrode (plate electrode), with a dielectric material between the two electrodes. The capacitance of the capacitor is proportional to the effective area of the electrodes and inversely proportional to the distance between the two electrodes, i.e., the thickness of the dielectric. Therefore, in order to increase capacitance, it is necessary to increase the effective capacitor area and/or decrease the thickness of the dielectric. Also, it is advantageous to have a dielectric with a high permittivity or dielectric constant.
Various methods have been proposed to provide a capacitance above a certain minimum threshold level. One such method of increasing the surface area of the semiconductor capacitor is to use the properties of material itself, for example, by forming the lower electrode of the capacitor with a HSG silicon layer. Such a technique is disclosed in H. Watanabe et al., "Hemispherical Grained Silicon Formation on In-Situ Phosphorous Doped Amorphous-Si Using The Seeding Method", SSDM'92 pp 422-424.
Briefly, the lower electrode of the DRAM capacitor is the part that stores information via electrons which are transferred through contact holes from a source area of MOS transistor. The lower electrode is formed on the semiconductor substrate, with an intermediate insulating film formed between the lower electrode and the substrate. A silicon oxide film is generally used as the intermediate insulating film.
The lower electrode is formed using, for example, phosphorous-doped amorphous silicon by low pressure chemical vapor deposition (CVD) techniques. After forming the lower electrode and the intermediate insulating film over the substrate, a lower electrode pattern is formed using conventional photolithography techniques know to those skilled in the art. Thereafter, the HSG silicon layer is formed over the exposed surface of the lower electrode pattern. The HSG silicon layer increases the surface area of the capacitor by relying on the fact that a hemisphere-shaped area is formed at the transition temperature ranges of crystalline-Si and amorphous-Si by silicon migration, with its surface energy being stable. The HSG forming method also relies on the fact that silicon gas groups, such as Si.sub.2 H.sub.6 and SiH.sub.4, have reactive surfaces, and that inner portions of the silicon layer form protrusions that serve as a seed for particles deposited during the CVD process, making the wafer surface rough. This roughened surface increases the effective surface area of the electrode which thereby increases the capacitance of the capacitor.
In the conventional process for forming a HSG silicon layer, a temperature stabilization step maintains a constant temperature, for example, 580.degree. C., inside a CVD apparatus having a high vacuum state. In a subsequent seeding step, a seeding gas comprised of molecules of Si.sub.2 H.sub.6 or SiH.sub.4 are irradiated on the surface of the exposed lower electrode, with the molecules exhibiting active surface reactions. Next, thermal treatment is carried out to form the HSG silicon layer. The surface of the HSG layer is thus characterized by concave and convex hemispherical shapes due to the thermal migration of silicon particles.
During manufacturing of a capacitor as described above, two kinds of loading methods for the wafer substrates are utilized. The first method is a single wafer loading method, in which each wafer to be processed is moved one by one. The second method is a batch type loading method, in which dozens of wafers are simultaneously moved. Although the former method is good for maintaining uniform processing conditions, it results in poor productivity. Thus, the latter batch type method is preferred since productivity is enhanced.
However, batch type loading is problematic because the particular processing conditions experienced by the wafers vary slightly due to the different positions of the wafers inside the processing chamber. Therefore, it is important to try and maintain uniform processing conditions across the entire wafer batch.
FIG. 1 is a schematic representation of a conventional semiconductor device fabrication apparatus incorporating a vertical low pressure chemical vapor deposition apparatus for use in the HSG formation process.
As shown in FIG. 1, a processing chamber 20 is vertically aligned with and disposed above a loadlock chamber 10. A gate valve 14 is installed between the processing chamber 20 and the loadlock chamber 10, and a boat 12 with wafers loaded thereon is placed inside the loadlock chamber 10.
The processing chamber 20 has a double tube structure, that is, an outer tube 26 being dome-shaped, with its top end sealed, covering an inner tube 24 with its top end open. A single gas supply nozzle 22 is disposed in the inner tube 24 and supplies a source gas through an opening in a flange 16 connecting the processing chamber 20 and the loadlock chamber 10.
The gas supply nozzle 22 includes a plurality of spray openings 23, spaced at equal intervals from each other. A heat block 28 encases the outer tube 26.
A vacuum system is installed to maintain the loadlock chamber 10 and the processing chamber 20 under vacuum. The vacuum system includes a loadlock chamber vacuum line 43, having an air valve 36, connected to a lower part of the loadlock chamber 10. The loadlock chamber vacuum line 43 is configured to discharge through the mechanical booster pump 30 and dry pump 32. The vacuum system also includes a processing chamber vacuum line 44, having an air valve 34, which is connected to the processing chamber 60 and is also configured to discharge through the mechanical booster pump 30 and dry pump 32.
FIG. 2 is a detailed representation of the vacuum system for the apparatus shown in FIG. 1. The processing chamber vacuum line 44 contains a bypass vacuum line, having an air valve 35 and a hand valve 33 installed thereon, connected on either side of the air valve 34. A purge gas supply line having flow meters 37 and 38, a check valve 41, and an air valve 40 are installed in order to clean mechanical booster pump 30 and dry pump 32. Another bypass line having an air valve 39 and a check valve 42 installed thereon, is oriented so as to bypass the mechanical booster pump 30 and the dry pump 32. A pirani gauge 45 for measuring pressure is installed before the mechanical booster pump 30.
Referring to FIG. 1 and FIG. 2, in the conventional HSG silicon formation process, a boat 12 loaded with wafers, each having a lower electrode thereon, is moved into the loadlock chamber 10 through the side wall of the loadlock chamber 10 by a wafer transportation means. Thereafter, contaminants and native oxide films are prevented from forming on the wafers by operating the vacuum line of the loadlock chamber 10 so as to maintain the loadlock chamber 10 under a nitrogen atmosphere in a high pressure or in a vacuum state. Then, gate valve 14 is opened, and boat 12 is transferred into the processing chamber 20 by an elevator (not shown).
After stabilizing the temperature of the processing chamber, the temperature of the processing chamber 20 is increased up to a designated level in order to maximize HSG nucleus generating conditions. The silicon group gas is supplied as seeding gas through the gas supply nozzle 22, and the thermal treatment for nuclei growth is performed by operating the processing chamber vacuum line so as to maintain the processing chamber in a high vacuum state.
After the HSG silicon layer is formed on the lower electrode of the capacitor, the boat 12 is moved back to the loadlock chamber 10 for cooling, and the process is complete.
The above conventional apparatus for manufacturing semiconductor devices using batch-type loading has good productivity, but the processing conditions are different throughout every position of the wafers inside the boat such that the processing results are not uniform throughout the wafers in the same batch. Also, for HSG nucleus growth, it takes too long a time to reach the desired vacuum state inside the processing chamber 20, so that silicon migration is difficult and the size of the hemispherical silicon nucleus is reduced.